The present invention relates to a semiconductor memory device, and more particularly, to a level shifter and a data output buffer having the level shifter adapted for use in a semiconductor memory device.
Conventional semiconductor memory devices are generally implemented in CMOS. CMOS memory devices operate at a lower speed than BiCMOS semiconductor memory devices. One reason for this difference is the fact that conventional BiCMOS memory devices process input signals at emitter-coupled logic (ECL) levels. However, when ECL-level signals are subsequently output a large output signal margin is required to operate with external circuitry. This requirement necessitates a level shifter to convert the ECL-level signals into CMOS levels for output from the semiconductor memory device.
FIG. 1 is a block diagram showing a conventional data output buffer in a semiconductor memory device. The data output buffer of FIG. 1 includes level shifters 1 and 3 which receive signals SAS and SAS (the inverse of SAS) at bipolar logic levels from a sense amplifier (not shown). Input signals SAS and SAS are level shifted by level shifters 1 and 3. The data output buffer of FIG. 1 also includes an output driver 2 for driving (boosting) the output voltages D1 and D2, the output of level shifters 1 and 2, respectively.
FIG. 2 is a more detailed circuit diagram of the level shifter shown in FIG. 1. Referring to FIG. 2, level shifter 1 or 3 comprises a PMOS transistor MP1 having a power supply voltage (Vcc) applied to its source, and SAS applied to its gate; a PMOS transistor MP2 having Vcc applied to its source, and SAS applied to its gate; an NMOS transistor MN1 having a drain and gate commonly connected to the drain of PMOS transistor MP1 and having a source connected to ground; an NMOS transistor MN2 having a drain connected to the drain of PMOS transistor MP2, having a gate connected to the gate of NMOS transistor MN1, and having a source connected to ground; an NMOS transistor MN3 having a gate connected to the gate of NMOS transistor MN2; an NMOS transistor MN4 having a drain connected to the source of NMOS transistor MN3, having a source connected to ground, and having a gate connected to the drain of NMOS transistor MN3; an NMOS transistor MN5 having an inverse output enable signal (OEB) applied to its gate, having a drain connected to the drain of NMOS transistor MN3, and having a source connected to the source of NMOS transistor MN3; an NPN transistor Q1 having a base connected to the drain of PMOS transistor MP2, having a collector connected to Vcc, and having an emitter connected to the drains of NMOS transistor MN3 and NMOS transistor MN5; an NPN transistor Q2 having a collector connected to the emitter of NPN transistor Q1, having a gate connected to the sources of NMOS transistors MN3 and MN5, and having an emitter connected to ground; a PMOS transistor MP3 having a gate receiving SAS, having a source connected to Vcc, and having a drain connected to the emitter of NPN transistor Q1; and, an inverter INV1 having an input connected to the drain of PMOS transistor MP3 and having an output forming terminal D1 or D2.
In level shifter 1, PMOS transistor MP3 is used to ensure that "high" (logic level) outputs reach a potential very near Vcc, since the use of NPN transistor Q1 alone may not accomplish this result. Similarly, NMOS transistors MN3, MN4 and MN5 are used to ensure that "low" outputs are at ground potential.
The operation of conventional data output buffers will be described below. In the following description SAS and SAS are assumed to be amplifier output signals from a bipolar sense amplifier designed to have a voltage swing width of approximately 1 V.
If the power supply voltage is 3 V and output signals SAS and SAS swing roughly from 1 V to 2 V, PMOS transistors MP1 and MP2 will always waste a certain amount of voltage. If output signal SAS is 1 V while inverse output signal SAS is 2 V, the current which flows via PMOS transistor MP1 is higher than that flowing via PMOS transistor MP2. This means that the current flowing through NMOS transistor MN2 and comprising a current mirror, is higher than that flowing through PMOS transistor MP2. Thus, the output of level shifter 1 drops to a low level.
On the contrary, if signal SAS is 2 V while signal SAS is 1 V, the current flowing through PMOS transistor MP2 is higher than that through NMOS transistor MN2. Therefore, the output of level shifter 1 rises to a high level. In other words, it is possible to provide a full swing output for inputs having a voltage swing width of 1 V to 2 V. When the output signal of level shifter 1 is input so as to drive NPN transistors Q1 and Q2, output signal D1 swings completely from a high level to a low level, to thereby operate output driver 2.
Output driver 2 shown in FIG. 2B comprises an NPN transistor Q6 receiving output D1 from level shifter 1, and an NMOS transistor MN6 receiving output D2 from level shifter 3. With this configuration output driver 2 performs a data buffering action according to the output of level shifters 1 and 3.
The foregoing conventional data output buffer is not without its problems. Input signals SAS and SAS often fluctuate from their nominal levels. For example, SAS may vary to 1.3 V and SAS may vary to 1.7 V. In such circumstances, PMOS transistors MP1 and MP2 consume excess current. Furthermore, the currents flowing respectively through PMOS transistors MP1 and MP2 become similar in their level. All of the foregoing necessarily reduces the power voltage operating range.